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| W48S87-72 Desktop/Notebook Frequency Generator Features * Maximized EMI suppression using Cypress's Spread Spectrum technology * 0.5% Spread Spectrum clocking * Equivalent to the W48S67-72 with Spread Spectrum for Tilamook, MMO, and Deschutes processors * Generates system clocks for CPU, IOAPIC, SDRAM, PCI, USB plus 14.318-MHz (REF0:1) * Serial data interface (SDATA, SCLOCK inputs) provides additional CPU/PCI clock frequency selections, individual output clock disabling and other functions * MODE input pin selects optional power management input control pins (reconfigures pins 26 and 27) * Two fixed outputs separately selectable as 24-MHz or 48-MHz (default = 48-MHz) * VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5% * Uses external 14.318-MHz crystal * Available in 48-pin SSOP (300 mils) * 10 CPU output impedance Table 1. Pin Selectable Frequency[1] 60/66_SEL 0 1 CPU, SDRAM Clocks (MHz) 60 66.8 PCI Clocks (MHz) 30 33.4 Block Diagram VDDQ3 REF0 X1 X2 XTAL OSC PLL Ref Freq VDDQ2 IOAPIC VDDQ2 CPU0 CPU_STOP# I/O Control Stop Output Control CPU1 CPU2 CPU3 VDDQ3 SDRAM0 SDRAM1 SDRAM2 60/66_SEL PLL 1 SDRAM3 SDRAM4 SDRAM5 /2 SDRAM6 SDRAM7 PCI_F Stop Output Control Power Down Control PCI0 PCI1 PCI2 PWR_DWN# PCI3 PCI4 PCI5 PLL2 48/24MHZ 48/24MHZ REF1 Pin Configuration REF1 REF0 GND X1 X2 MODE VDDQ3 PCI_F PCI0 GND PCI1 PCI2 PCI3 PCI4 VDDQ3 PCI5 GND 60/66_SEL SDATA SCLOCK VDDQ3 48/24MHZ 48/24MHZ GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ3 CPU2.5# VDDQ2 IOAPIC PWR_DWN# GND CPU0 CPU1 VDDQ2 CPU2 CPU3 GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6/CPU_STOP# SDRAM7/PCI_STOP# VDDQ3 W48S87-72 MODE Note: 1. Additional frequency selections provided by serial data interface; refer to Table 5 on page 8. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 August 4, 2000 rev. *A W48S87-72 Pin Definitions Pin Name CPU0:3 Pin No. 42, 41, 39, 38 9, 11, 12, 13, 14, 16 8 Pin Type O Pin Description CPU Outputs 0 through 3: These four CPU outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI Bus Outputs 0 through 5: These six PCI outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Free Running PCI Output: Unlike PCI0:5 outputs, this output is not controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. SDRAM Clock Outputs 0 through 5: These six SDRAM clock outputs run synchronous to the CPU clock outputs. Output voltage swing is controlled by voltage applied to VDDQ3. SDRAM Clock Output 6 or CPU Clock Output Stop Control: This pin has dual functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the CPU_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 6. Regarding use as a CPU_STOP# input: When brought LOW, clock outputs CPU0:3 are stopped LOW after completing a full clock cycle (2-3 CPU clock latency). When brought HIGH, clock outputs CPU0:3 are started beginning with a full clock cycle (2-3 CPU clock latency). Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage applied to VDDQ3. SDRAM7/ PCI_STOP# 26 I/O SDRAM Clock Output 7 or PCI Clock Output Stop Control: This pin has dual functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the PCI_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 7. PCI_STOP# input: When brought LOW, clock outputs PCI0:5 are stopped LOW after completing a full clock cycle. When brought HIGH, clock outputs PCI0:5 are started beginning with a full clock cycle. Clock latency provides one PCI_F rising edge of PCI clock following PCI_STOP# state change. Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage applied to VDDQ3. IOAPIC 48/24MHz 45 22, 23 O O I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. 48-MHz / 24-MHz Output: Fixed clock outputs that default to 48 MHz following device power-up. Either or both can be changed to 24 MHz through use of the serial data interface (Byte 0, bits 2 and 3). Output voltage swing is controlled by voltage applied to VDDQ3 Fixed 14.318-MHz Outputs 0 through 1: Used for various system applications. Output voltage swing is controlled by voltage applied to VDDQ3. REF0 is stronger than REF1 and should be used for driving ISA slots. Set to logic 0 for V DDQ2 = 2.5V (0 to 2.5V CPU output swing). 60- or 66-MHz Input Selection: Selects power-up default CPU clock frequency as shown in Table 1 on page 1 (also determines SDRAM and PCI clock frequency selections). Can be used to change CPU clock frequency while device is in operation if serial data port bits 0-2 of Byte 7 are logic 1 (default powerup condition). Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. PCI0:5 O PCI_F O SDRAM0:5 36, 35, 33, 32, 30, 29 27 O SDRAM6/ CPU_STOP# I/O REF0:1 2, 1 O CPU_2.5# 60/66_SEL 47 18 I I X1 4 I X2 5 I 2 W48S87-72 Pin Definitions (continued) Pin Name PWR_DWN# Pin No. 44 Pin Type I Pin Description Power-Down Control: When this input is LOW, the device goes into a lowpower standby condition. All outputs are actively held LOW while in powerdown. CPU, SDRAM, and PCI clock outputs are stopped LOW after completing a full clock cycle (2-4 CPU clock cycle latency). When brought HIGH, CPU, SDRAM, and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). Mode Control: This input selects the function of device pin 26 (SDRAM7/PCI_STOP#) and pin 27 (SDRAM6/CPU_STOP#). Refer to description for those pins. Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data Interface section that follows. Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data Interface section that follows. Power Connection: Power supply for PCI0:5, REF0:1, and 48/24MHz output buffers. Connected to 3.3V supply. Power Connection: Power supply for IOAPIC0, CPU0:3 output buffer. Connected to 2.5V supply. Ground Connection: Connect all ground pins to the common system ground plane. MODE 6 I SDATA SCLOCK VDDQ3 VDDQ2 GND 19 20 7, 15, 21, 25 28, 34, 48 46, 40 3, 10, 17, 24, 31, 37, 43 I/O I P P G 3 W48S87-72 Spread Spectrum Generator The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1. As depicted in Figure 1, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F) Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. G%GLY The output clock is modulated with a waveform depicted in Figure 2. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is 0.5% of the center frequency. Figure 2 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1-0 in data byte 0 of the I2C data stream. Refer to Table 4 for more details. 66)7* $PSOLWXGH G% 7\SLFDO &ORFN 6SUHDG 6SHFWUXP (QDEOHG (0, 5HGXFWLRQ 43 6SHFWUXP $570,/ 66 )UHTXHQF\ 6SDQ 0+] 66 66 )UHTXHQF\ 6SDQ 0+] Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation MAX (+.0.5%) FREQUENCY 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% MIN. (-0.5%) Figure 2. Typical Modulation Profile 4 100% W48S87-72 Serial Data Interface The W48S87-72 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W48S87-72 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is writeonly (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs Table 2. Serial Data Interface Control Functions Summary Control Function Clock Output Disable Description Common Application Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused SDRAM DIMM socket or PCI slot. 48-/24-MHz clock outputs can be set to 48 MHz or 24 MHz. Provides CPU/PCI frequency selections beyond the 60- and 66.6-MHz selections that are provided by the SEL60/66 input pin. Frequency is changed in a smooth and controlled fashion. Puts all clock outputs into a high-impedance state. All clock outputs toggle in relation with X1 input, internal PLL is bypassed. Refer to Table 4. Provides flexibility in Super I/O and USB device selection. For alternate CPU devices, and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Production PCB testing. Production PCB testing. of the chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface. Operation Data is written to the W48S87-72 in ten bytes of eight bits each. Bytes are written in the order shown in Table 3. 48-/24-MHz Clock Output Frequency Selection CPU Clock Frequency Selection Output Three-state Test Mode (Reserved) Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0. Table 3. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the W48S87-72 to accept the bits in Data Bytes 0-7 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W48S87-72 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W48S87-72, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W48S87-72, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in Data Bytes 0-7 set internal W48S87-72 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map. 2 Command Code Don't Care 3 Byte Count Don't Care 4 5 6 7 8 9 10 11 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Refer to Table 4 5 W48S87-72 Writing Data Bytes Each bit in the data bytes control a particular device function except for the "reserved" bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit Table 4. Data Bytes 0-7 Serial Configuration Map Affected Pin Bit(s) 7 6 5 4 3 2 1-0 Pin No. ----23 22 -Pin Name ----48/24MHZ 48/24MHZ -(Reserved) (Reserved) SEL_4 SEL_3 48-/24-MHz Clock Output Frequency Selection 48-/24-MHz Clock Output Frequency Selection Bit 1 0 0 1 1 Bit 0 0 1 0 1 Control Function 0 -Data Byte 0 -0 0 0 0 0 0 00 Refer to Table 5 Refer to Table 5 Refer to Table 5 24 MHz 24 MHz 48 MHz 48 MHz Bit Control 1 Default 7. Table 4 gives the bit formats for registers located in Data Bytes 0-7. Table 5 details additional frequency selections that are available through the serial data interface. Table 6 details the select functions for Byte 0, bits 1 and 0. Function (See Table 6 for function details) Normal Operation Test Mode Spread Spectrum On All Outputs Three-stated Low Low --Low Low Low Low -Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Active Active --Active Active Active Active -Active Active Active Active Active Active Active Active Active Active Active Active Active Active Active Data Byte 1 7 6 5 4 3 2 1 0 Data Byte 2 7 6 5 4 3 2 1 0 Data Byte 3 7 6 5 4 3 2 1 0 26 27 29 30 32 33 35 36 SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 1 1 1 1 1 1 1 1 -8 16 14 13 12 11 9 -PCI_F PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 0 1 1 1 1 1 1 1 23 22 --38 39 41 42 48/24MHZ 48/24MHZ --CPU3 CPU2 CPU1 CPU0 Clock Output Disable Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 1 1 0 0 1 1 1 1 6 W48S87-72 Table 4. Data Bytes 0-7 Serial Configuration Map (continued) Affected Pin Bit(s) 7 6 5 4 3 2 1 0 Data Byte 5 7 6 5 4 3 2 1 0 Data Byte 6 7 6 5 4 3 2 1 0 Data Byte 7 7 6 5 4 3 2 1 0 ----------------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) SEL_2 SEL_1 SEL_0 ----------0 0 0 0 0 1 1 1 ----------------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ----------------0 0 0 0 0 0 0 0 ---45 --1 2 ---IOAPIC --REF1 REF0 (Reserved) (Reserved) (Reserved) Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable ---Low --Low Low ---Active --Active Active 0 0 0 1 0 0 1 1 Pin No. --------Pin Name --------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Control Function 0 --------Data Byte 4 --------0 0 0 0 0 0 0 0 Bit Control 1 Default Refer to Table 5 Refer to Table 5 Refer to Table 5 7 W48S87-72 Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Date Byte 0 Bit 5 SEL_4 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bit 4 SEL_3 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 60/66_SEL (Pin 18) X X X X X X X 0 1 0 1 0 1 0 1 Bit 2 SEL_2 0 0 0 0 1 1 1 1 1 X X X X X X Date Byte 7 BIT 1 SEL_1 0 0 1 1 0 0 1 1 1 X X X X X X BIT 0 SEL_0 0 1 0 1 0 1 0 1 1 X X X X X X CPU0:3 SDRAM0:7 75.0 75.0 83.31 33.41 50.11 68.52 60.0 60.0 66.82 60.0 66.6 60.0 66.6 60.0 66.6 PCI_F PCI0:5 CPU/2 32 32 CPU/2 CPU/2 CPU/2 CPU/2 CPU/2 CPU/2 CPU/2 CPU/2 CPU/2 CPU/2 CPU/2 CPU/2 Spread Spectrum% 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 -0.5 0.5 -0.5 0.5 -0.5 Table 6. Select Function for Data Byte 0, Bits 0:1 Input Conditions Data Byte 0 Function Normal Operation Test Mode Spread Spectrum On Three-state Bit 1 0 0 1 1 Bit 0 0 1 0 1 CPU0:3, SRAM0:7 Note 2 X1/2 Note 2 Hi-Z Output Conditions PCI_F, PCI0:5 Note 2 X1/4 Note 2 Hi-Z REF0:2, IOAPIC 14.318 MHz X1 14.318 MHz Hi-Z 48/24MHZ 48 or 24 MHz Note 3 48 or 24 MHz Hi-Z Notes: 2. CPU, SDRAM, and PCI frequency selections are listed in Table 1 and Table 5. 3. In Test Mode, the 48-/24-MHz clock outputs are: - X1/2 if 48-MHz is selected. - X1/4 if 24-MHz is selected. 8 W48S87-72 How To Use the Serial Data Interface Electrical Requirements Figure 3 illustrates electrical characteristics for the serial interface bus used with the W48S87-72. Devices send data over the bus with an open drain logic output that can (a) pull the bus line LOW, or (b) let the bus default to logic 1. The pull-up resistors on the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data. 9'' Although the W48S87-72 is a receive-only device (no data write-back capability), it does transmit an "acknowledge" data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance. 9'' a N 6(5,$/ %86 '$7$ /,1( a N 6(5,$/ %86 &/2&. /,1( 6'&/. 6'$7$ 6&/2&. 6'$7$ &/2&. ,1 '$7$ ,1 &/2&. ,1 '$7$ ,1 &/2&. 287 1 '$7$ 287 1 '$7$ 287 1 &+,3 6(7 6(5,$/ %86 0$67(5 75$160,77(5 &/2&. '(9,&( 6(5,$/ %86 6/$9( 5(&(,9(5 Figure 3. Serial Interface Bus Electrical Characteristics 9 W48S87-72 Signaling Requirements As shown in Figure 4, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1) pulse. A transitioning data line during a clock HIGH pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). A write sequence is initiated by a "start bit" as shown in Figure 5. A "stop bit" signifies that a transmission has ended. As stated previously, the W48S87-72 sends an "acknowledge" pulse after receiving eight data bits in each byte as shown in Figure 6. Sending Data to the W48S87-72 The device accepts data once it has detected a valid start bit and address byte sequence. Device functionality is changed upon the receipt of each data bit (registers are not double buffered). Partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). Transmission is truncated with either a stop bit or new start bit (restart condition). 6'$7$ 6&/2&. 9DOLG 'DWD %LW &KDQJH RI 'DWD $OORZHG Figure 4. Serial Data Bus Valid Data Bit 6'$7$ 6&/2&. 6WDUW %LW Figure 5. Serial Data Bus Start and Stop Bit 6WRS %LW 10 Figure 6. Serial Data Bus Write Sequence 6LJQDOLQJ IURP 6\ VWHP &RUH /RJLF 6WDUW &RQGLWLRQ 6ODYH $GGUHVV )LUVW %\ WH &RPPDQG &RGH 6HFRQG %\WH %\ WH &RXQW 7KLUG %\WH /DVW 'DWD %\ WH /DVW %\WH 6WRS &RQGLWLRQ 6'$7$ 06% /6% 06% /6% 06% 06% /6% 6&/2&. $ $ $ 6'$7$ $FNQRZOHGJPHQW %LW IURP &ORFN 'HY LFH 6LJQDOLQJ E\ &ORFN 'HYLFH 11 Figure 7. Serial Data Bus Timing Diagram 6'$7$ W W 6&/2&. W 63) /2: W W '68 W '+' W 63 W 67+' W +,*+ W 6368 W 67+' W 5 ) 6368 W48S87-72 W48S87-72 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 2 (min.) Unit V C C C kV Parameter VDD, VIN TSTG TA TB ESDPROT Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5% (3.135-3.465V) fXTL = 14.31818 MHz, VDDQ2 = 2.55% Parameter Supply Current IDDQ3 IDDQ2 Logic Inputs VIL VIH IIL IIH VOL VOH VOH IOL Input Low Voltage Input High Voltage Input Low Current [5] [5] Description Supply Current (3.3V) Supply Current (2.5V) Test Condition CPUCLK =66.8 MHz Outputs Loaded[4] CPUCLK =66.8 MHz Outputs Loaded[4] Min. 120 Typ. 150 Max. 200 50 Unit mA mA 0.8 2.0 10 10 IOL = 1 mA IOH = -1 mA IOH = -1 mA VOL = 1.25V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.5V VOL = 1.5V CPU0:3 SDRAM0:7 IOAPIC REF0 REF1 48/24MHZ 3.1 2.2 155 100 95 85 75 60 60 125 95 100 80 80 65 60 50 V V A A mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA Input High Current Clock Outputs Output Low Voltage Output High Voltage Output High Voltage (CPU, IOAPIC) Output Low Current PCI_F, PCI0:5 VOL = 1.5V IOH Output High Current CPU0:3 SDRAM0:7 IOAPIC REF0 REF1 48/24MHZ PCI_F, PCI0:5 VOL = 1.5V Notes: 4. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section. 5. W48S87-72 logic inputs have internal pull-up devices. (Not CMOS level.) 12 W48S87-72 DC Electrical Characteristics: (continued) TA = 0C to +70C, VDDQ3 = 3.3V5% (3.135-3.465V) fXTL = 14.31818 MHz, VDDQ2 = 2.55% Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN VIL VIH IIL IIH IOL CIN CSDATA CSCLOCK X1 Input Threshold Voltage[6] Load Capacitance, Imposed on External Crystal[7] X1 Input Capacitance[8] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Input Low Voltage Input High Voltage Input Low Current Input High Current Sink Current into SDATA or SCLOCK, Open Drain N-Channel Device On Input Capacitance of SDATA and SCLOCK Total Capacitance of SDATA Bus Total Capacitance of SCLOCK Bus VDD = 3.3V VDD = 3.3V No internal pull-up/down on SCLOCK No internal pull-up/down on SCLOCK IOL = 0.3VDD 5 0.7VDD 0.4 2.4 10 10 10 5 10 10 15 10 400 400 Pin X2 unconnected Except X1 and X2 VDD = 3.3V 1.65 14 28 5 6 7 0.3VDD V pF pF pF pF nH V V A A mA pF pF pF Description Test Condition Min. Typ. Max. Unit Pin Capacitance/Inductance Serial Input Port Notes: 6. X1 input threshold voltage (typical) is VDDQ3 /2. 7. The W48S87-72 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 13 W48S87-72 AC Electrical Characteristics TA = 0C to +70C, VDD = VDDQ3 = 3.3V5% (3.135-3.465V) fXTL = 14.31818 MHz, VDDQ2 = 2.55% AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF) CPU = 66.8 MHz Parameter tP f tH tL tR tF tD tJC Description Period Frequency, Actual High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 10 5.2 5 1 1 45 52 4 4 55 250 Min. 15 66.8 6 5.8 1 1 45 52 4 4 55 250 CPU = 60 MHz Typ. Max. Unit ns 59.876 MH z ns ns V/ns V/ns % ps 16.7 Typ. Max. Min. Output Rise Edge Rate Measured from 0.4V to 2.4V tSK fST Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance 250 3 250 3 ps ms Zo 10 SDRAM Clock Outputs, SDRAM0:7 (Lump Capacitance Test Load = 30 pF) CPU = 66.8 MHz Parameter tP f tR tF tD tJC Description Period Frequency, Actual Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio 1 1 45 50 Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/SDRAM outputs. Measured on rising edge at 1.5V. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 16 100 500 3 Min. 15 66.8 4 4 55 250 1 1 45 50 CPU = 60 MHz Typ. Max. Unit ns 59.876 4 4 55 250 MHz V/ns V/ns % ps 16.7 Typ. Max. Min. Output Rise Edge Rate Measured from 0.4V to 2.4V tSK tSK fST Output Skew CPU to SDRAM Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance 100 500 3 ps ps ms Zo 16 14 W48S87-72 PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF) CPU = 66.8 MHz Parameter tP f tH tL tR tF tD tJC Description Period Frequency, Actual High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 30 1 Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V 12 12 1 1 45 51 4 4 55 250 Min. 30 33.4 13.3 13.3 1 1 45 51 4 4 55 250 CPU = 60 MHz Typ. Max. Unit ns 29.938 MHz ns ns V/ns V/ns % ps 33.3 Typ. Max. Min. tSK tO Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance 250 4 1 250 4 ps ns fST 3 3 ms Zo 30 I/O APIC Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 60/66.8 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Measured on rising and falling edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 Test Condition/Comments Frequency generated by crystal oscillator 1 1 45 52.5 Min. Typ. 14.31818 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms Zo 15 W48S87-72 REF0 Clock Output (Lump Capacitance Test Load = 45 pF) CPU = 60/66.8 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V 1 1 45 50 Min. Typ. 14.31818 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 16 Zo REF1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 60/66.8 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 Test Condition/Comments Frequency generated by crystal oscillator 0.5 0.5 45 Min. Typ. 14.31818 2 2 55 1.5 Max. Unit MHz V/ns V/ns % ms Zo 48/24MHZ Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 60/66.8 MHz Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Measured on rising and falling edge at 1.5V Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 40 Test Condition/Comments Determined by PLL divider ratio (see n/m below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) 0.5 0.5 45 50 Min. Typ. Max. Unit MHz ppm 2 2 55 3 V/ns V/ns % ms 48.008/24.004 +167 57/17 Zo 16 W48S87-72 Serial Input Port Parameter fSCLOCK tSTHD tLOW tHIGH tDSU tDHD tR tF tSTSU tSPF tSP Description SCLOCK Frequency Start Hold Time SCLOCK Low Time SCLOCK High Time Data Set-up Time Data Hold Time Rise Time, SDATA and SCLOCK Fall Time, SDATA and SCLOCK Stop Set-up Time Bus Free Time between Stop and Start Condition Allowable Noise Spike Pulse Width (Transmitter should provide a 300-ns hold time to ensure proper timing at the receiver.) From 0.3VDD to 0.7VDD From 0.7VDD to 0.3VDD 4.0 4.7 50 Test Condition Normal Mode Min. 0 4.0 4.7 4.0 250 0 1000 300 Typ. Max. 100 Unit kHz s s s ns ns ns ns s s ns Ordering Information Ordering Code W48S87 Document #: 38-00855-*A Freq. Mask Code 72 Package Name H X Package Type 48-pin SSOP (300 mils) 48-pin TSSOP 17 W48S87-72 Package Diagrams 48-Pin Small Shrink Outline Package (SSOP, 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102 18 W48S87-72 Package Diagrams (continued) 48-Pin Thin Shrink Small Outline Package (TSSOP) 12 11 10 9 8 7 6 5 4 3 2 1 H H THIS TABLE IN MILLIMETERS S Y M B O L G COMMON DIMENSIONS NOM. MIN. MAX. 0.10 0.05 0.90 0.85 0.17 0.17 0.20 0.090 0.090 0.127 SEE VARIATIONS 6.00 6.10 0.50 BSC 7.95 8.10 0.50 0.60 SEE VARIATIONS 1.10 0.15 0.95 0.27 0.23 0.200 0.160 6.20 8.25 0.75 N O T E NOTE VARIATIONS AA AB MIN. 12.40 13.90 4 D NOM. 12.50 14.00 MAX. 12.60 14.10 MIN. 0.37 0.12 S NOM. 0.50 0.25 6 N MAX. 48 56 G F A A1 A2 b b1 C C1 D E 8 8 4 4 F e E C OC H L N 5 6 E 0 4 8 THIS TABLE IN INCHES D S Y M B O L D COMMON DIMENSIONS MIN. MAX. NOM. .002 .004 .0354 .0335 .0067 .0067 .0078 .0035 .0035 .0050 SEE VARIATIONS .236 .240 .0197 BSC .313 .319 .020 .024 SEE VARIATIONS .0433 .006 .0374 .011 .0090 .0078 .0063 .244 .325 .030 N O T E NOTE VARIATIONS AA AB MIN. .488 .547 4 D NOM. .492 .551 MAX. .496 .555 MIN. .0146 .0047 S NOM. .0197 .0098 6 N MAX. 48 56 C C B A A1 A2 b b1 C C1 D E 8 8 4 4 e B C OC H L N 5 6 TITLE 0 4 8 P AC KA G E O UTLINE , 6 .10 mm (.2 40 ") B O DY, TSS O P, 0.50 mm L EA D P ITC H SIZE D WG. N O. A A R EV . A1 SC AL E 34389 S HE ET 02 2 OF 2 1 8/1 2 12 11 10 9 8 7 6 5 4 3 (c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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